// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

module A_cse_ocs_dpa_aes10c_gf16_sq_sbox_withmap (
   input  logic [7:0]  in,
   output logic [7:0]  out );

   wire [7:0]   gfinv_in;
   wire [7:0]   gfinv_out;

   localparam POLY1 = 9;
   localparam ALPHA = 1;
   localparam BETA = 8;

   localparam MAP_ROW7 = 8'b11010010;
   localparam MAP_ROW6 = 8'b01111110;
   localparam MAP_ROW5 = 8'b00001100;
   localparam MAP_ROW4 = 8'b11010000;
   localparam MAP_ROW3 = 8'b00001000;
   localparam MAP_ROW2 = 8'b00100100;
   localparam MAP_ROW1 = 8'b11100110;
   localparam MAP_ROW0 = 8'b11000111;

   localparam COMBINEDAFFINE_MAP_ROW7 = 8'b00110100;
   localparam COMBINEDAFFINE_MAP_ROW6 = 8'b11010000;
   localparam COMBINEDAFFINE_MAP_ROW5 = 8'b00011010;
   localparam COMBINEDAFFINE_MAP_ROW4 = 8'b00011001;
   localparam COMBINEDAFFINE_MAP_ROW3 = 8'b01010011;
   localparam COMBINEDAFFINE_MAP_ROW2 = 8'b00000001;
   localparam COMBINEDAFFINE_MAP_ROW1 = 8'b00000101;
   localparam COMBINEDAFFINE_MAP_ROW0 = 8'b00010011;

   localparam AFFINE_B = 8'b01100011;

  //Matrix compuates Map only
   A_cse_ocs_dpa_aes10c_map #(
                   .MAP_ROW7(MAP_ROW7 ),
                   .MAP_ROW6(MAP_ROW6 ),
                   .MAP_ROW5(MAP_ROW5 ),
                   .MAP_ROW4(MAP_ROW4 ),
                   .MAP_ROW3(MAP_ROW3 ),
                   .MAP_ROW2(MAP_ROW2 ),
                   .MAP_ROW1(MAP_ROW1 ),
                   .MAP_ROW0(MAP_ROW0 ))
           map ( .in(in), .out(gfinv_in));

   A_cse_ocs_dpa_aes10c_gf16_sq_inv #(.BETA(BETA), .ALPHA(ALPHA), .POLY1(POLY1)) gf16 (
		     .sh_in_rxs  ( gfinv_in[7:4] ),
		     .sl_in_rxs  ( gfinv_in[3:0] ),
		     .sh_out_wxs ( gfinv_out[7:4] ),
		     .sl_out_wxs ( gfinv_out[3:0] )
		     );
   
   A_cse_ocs_dpa_aes10c_affine #(.AFFINE_MAP_ROW7(COMBINEDAFFINE_MAP_ROW7),
            .AFFINE_MAP_ROW6(COMBINEDAFFINE_MAP_ROW6),
            .AFFINE_MAP_ROW5(COMBINEDAFFINE_MAP_ROW5),
            .AFFINE_MAP_ROW4(COMBINEDAFFINE_MAP_ROW4),
            .AFFINE_MAP_ROW3(COMBINEDAFFINE_MAP_ROW3),
            .AFFINE_MAP_ROW2(COMBINEDAFFINE_MAP_ROW2),
            .AFFINE_MAP_ROW1(COMBINEDAFFINE_MAP_ROW1),
            .AFFINE_MAP_ROW0(COMBINEDAFFINE_MAP_ROW0),
            .MB(AFFINE_B))
           
           A ( .in(gfinv_out), .out(out));

   
endmodule // gf16_sq_sbox_enc

